The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Memory systems are susceptible to errors and failures. For example, some or all of the data stored on a particular allocation unit (AU) on a FLASH may become corrupted or otherwise inaccessible. Absent an appropriate error correction mechanism, a memory controller may not be able to recover the lost data. To alleviate this problem, the memory controller may introduce error correcting capabilities in the coding process, such as by encoding the data with an error correcting code (ECC) to make use of redundancy in order to correct errors.
However, the error correcting capability of a given ECC is limited by the amount of redundant bits allowable in the system. As the number of memory failures (or errors) increases, it becomes computationally and spatially expensive to keep adding redundancy to the ECC scheme.